H3DNAS: Hardware-Aware ONNX-Native 3D Point Cloud Model Compression
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Computer Science > Machine Learning
arXiv:2609.02684 (cs)
[Submitted on 2 Sep 2026]
Title:H3DNAS: Hardware-Aware ONNX-Native 3D Point Cloud Model Compression
View a PDF of the paper titled H3DNAS: Hardware-Aware ONNX-Native 3D Point Cloud Model Compression, by Anchit Mulye and 3 other authors
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Abstract:Deploying 3D point cloud models on edge hardware such as the NVIDIA Jetson Orin Nano is severely constrained by compute and memory budgets. Existing compression methods require access to the model's original source code, rendering them inapplicable to the Open Neural Network Exchange (ONNX) binaries commonly distributed by vendors and model repositories. We present \textbf{H3DNAS}, a hardware-aware model compression framework that operates directly on ONNX computational graphs without requiring original source code, architecture class definition, or gradient access during search. H3DNAS makes three contributions: (1) a \textbf{Channel Dependency Graph (CDG)} that classifies ONNX operators into four constraint classes and formally establishes that the free parameter fraction $\rho_f$ is topological invariant, a provable compression ceiling computable in $\mathcal{O}(|V|+|E|)$; (2) a \textbf{Two-Stage Hierarchical Search} that prunes candidate architectures by $L_1$-importance channel selection, ranks them by output fidelity as a zero-shot label-free proxy, and applies GhostConv structural mutation to Pareto-optimal candidates; and (3) the \textbf{first source-code-free compression pipeline for 3D point cloud models}, operating entirely via ONNX graph surgery with no original architecture definition required. On ModelNet40, H3DNAS reduces the number of parameters in PointNet, PointNet++, and PointMLP by $65.5\%$, $43.2\%$, and $49.1\%$, respectively, while achieving $1.99\times$, $1.29\times$, and $1.67\times$ inference speedups with negligible loss in accuracy. The source code is publicly available\footnote{this https URL}.
| Subjects: | Machine Learning (cs.LG); Hardware Architecture (cs.AR); Neural and Evolutionary Computing (cs.NE) |
| Cite as: | arXiv:2609.02684 [cs.LG] |
| (or arXiv:2609.02684v1 [cs.LG] for this version) | |
| https://doi.org/10.48550/arXiv.2609.02684
arXiv-issued DOI via DataCite (pending registration)
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